Field of the Invention
The present invention relates to imaging devices and imaging systems, and more particularly to an imaging device having disposed therein plural unit cells including plural photoelectric conversion regions, plural transfer switch means provided corresponding to the plural photoelectric conversion regions, respectively, and common amplification means which amplifies and outputs signals read from the plural photoelectric conversion regions.
Related Background Art
In recent years, imaging devices called a CMOS sensor using CMOS process are attracting attention. By virtue of integratability of peripheral circuitry, low-voltage drive, and so on, the CMOS sensor is being increasingly applied particularly to the field of mobile information devices.
As a pixel configuration of CMOS sensors with a high S/N ratio, for example, there has been known one in which a transfer switch is disposed between a photodiode and the input of a pixel amplifier as disclosed in Japanese Patent Application Laid-Open No. H11-122532. However, the drawbacks of this pixel configuration include a fact that since the number of transistors is large, when the pixel is scaled down, it is difficult to secure a sufficient area for the photodiode under constraint of the area required for the transistor. In order to overcome this disadvantage, there has recently been known a configuration in which plural adjacent pixels share a transistor, as disclosed, for example, in Japanese Patent Application Laid-Open No. H09-046596 (corresponding to U.S. Pat. No. 5,955,753). FIG. 12 (identical to FIG. 8 in the same patent application) shows the imaging device of conventional art. In the drawing, reference numeral 3 denotes a transfer MOS transistor acting as a transfer switch; 4 a reset MOS transistor which supplies a reset potential; 5 a source-follower MOS transistor; 6 a horizontal selecting MOS transistor for selectively allowing the source-follower MOS transistor 5 to output a signal; 7 a source-follower load MOS transistor; 8 a dark output transfer MOS transistor for transferring a dark output signal; 9 a bright output transfer MOS transistor for transferring a bright output signal; 10 a dark output accumulation capacitor CTN for accumulating the dark output signal; 11 a bright output accumulation capacitor CTS for accumulating the bright output signal; 12 a horizontal transfer MOS transistor for transferring the dark output signal and bright output signal to a horizontal output line; 13 a horizontal output line reset MOS transistor for resetting the horizontal output line; 14 a differential output amplifier; 15 a horizontal scanning circuit; 16 a vertical scanning circuit; 24 an embedded photodiode. Here, the dark output signal is a signal generated by resetting the gate region of the source-follower MOS transistor 5; the bright output signal is a signal obtained by combining a signal obtained by photoelectric conversion using the photodiode 24 and the dark output signal. From the differential output amplifier, there is obtained a signal with reduced fluctuation of the source-follower MOS transistor 5.
As evident from the drawing, one source-follower MOS transistor 5 is connected to two photodiodes 24 disposed in a vertical direction via transfer MOS transistors 3. Accordingly, while eight MOS transistors are required for two pixels in the conventional art, it is sufficient to provide five MOS transistors, thus being advantageous in miniaturization. By sharing the transistor, the number of transistors per pixel is reduced, whereby the area for the photodiode can be sufficiently secured.
Also, as an exemplary pixel layout of the shared-transistor configuration, there is one disclosed in Japanese Patent Application Laid-Open No. 2000-232216 (corresponding to EP1017106A).
The present inventor has found that, in the above described CMOS sensor having a shared-transistor configuration disclosed in Japanese Patent Application Laid-Open No. H09-046596, a sensitivity difference between pixels is more likely to arise relative to the CMOS sensor having a non-shared-transistor configuration disclosed in Japanese Patent Application Laid-Open No. H11-122532.
An object of the present invention is to prevent the sensitivity difference while realizing miniaturization by a shared-transistor configuration.